NDLI: Perspective of FinFETs for analog applications

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On ambient intelligence, needful things and process technologies

Low power digital circuit design

Integrated circuits for the biology-to-silicon interface

Low voltage and low power aspects of data converter design

Technology considerations for automotive

Invited papers [breaker page]

Novel gate concepts for MOS devices

Linking technology-CAD and physical design

Integration of photonic functions in and with silicon

I contributed papers

Perspective of FinFETs for analog applications

FinFET SRAM for high-performance low-power applications

Demonstration of threshold voltage control techniques for vertical-type 4-terminal double-gate MOSFETs (4T-DGFET)

Experimental comparison between double gate, ground plane, and single gate SOI CMOSFETs

Space-charge-limited current conductions in La/sub 2/O/sub 3/ thin films deposited by e-beam evaporation after low temperature dry-nitrogen annealing [gate oxide applications]

Work function stability of thermal ALD Ta(Si)N gate electrodes on HfO/sub 2/ [CMOS device applications]

Characterization of Vt instability in hafnium based dielectrics by pulse gate voltage techniques [CMOS device applications]

Time-dependent dielectric breakdown of HfAlOx/SiON gate dielectric

A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack

High resolution two-dimensional carrier profiling on sub-100nm silicon nano-devices using scanning spreading resistance microscopy

Stresses in copper blanket films and damascene lines : measurements and finite element analysis

Mobility issues in ultra-thin SOI MOSFETs: thickness variations, GIFBE and coupling effects

Gate-capacitance extraction from RF C-V measurements [MOS device applications]

Back-etched super-junction LDMOST on SOI

A two mask complementary LDMOS module integrated in a 0.25 /spl mu/m SiGe:C BiCMOS platform

Source-gated transistors for thin film electronics

Integrated micro-channel cooling in silicon

Successful integration of an ultra low thermal budget process solution based on solid phase epitaxy for sub-50nm CMOS technologies

Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

Electrical analysis on the drain current of the ultra shallow junction by laser annealing

Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

Effects of wet cleaning treatment on dose of impurity after plasma doping

Thermal scaling of ultra-thin SOI: reduced resistance at low temperature RTA

Magnetoresistance mobility measurements in sub 0.1 /spl mu/m Si MOSFETs

Effect of high-k materials in the control dielectric stack of nanocrystal memories

A comprehensive study of corner effects in tri-gate transistors

Analysis of strained-silicon-on-insulator double-gate MOS structures

Double gate silicon-on-insulator transistors: n/sup +/-n/sup +/ gate versus n/sup +/-p/sup +/ gate configuration

A new approach to the self-consistent solution of the Schrodinger-Poisson equations in nanowire MOSFETs

Study of electrically active defects in high mobility HfO/sub 2/ MOSFETs

Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

Physical modeling and prediction of the matching properties of MOSFETs

Low temperature process flow optimisation for 65nm CMOS mixed-signal applications

101 GHz f/sub Tmax/ SiGe:C HBT integrated into 0.25 /spl mu/m CMOS with conventional LOCOS isolation

Dynamic latchup study using transmission line pulses and picosecond imaging circuit analysis [CMOS IC latchup]

Experimental evidence and statistical modeling of cooperating defects in stressed oxides [FLASH memory example]

Plasma process induced damage during via etching on PDMOS transistors

Depletion-all-around in SOI G/sup 4/-FETs: a conduction mechanism with high performance

CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance

Channel engineering towards a full low temperature process solution for the 45 nm technology node [NMOS transistors]

Programmable virtual source/drain MOSFETs

Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions

Investigations on possible occurrence of ballistic transport in different NMOS architectures

Vertical tunnel field-effect transistor with bandgap modulation and workfunction engineering

Investigation about the high-temperature impact-ionization coefficient in silicon

Electrostatic effect of localised charge in dual bit memory cells with discrete traps

Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors

NBTI reliability analysis for a 90 nm CMOS technology

ESD protection of double-diffusion devices in submicron CMOS processes

New methodologies of NBTI characterization eliminating recovery effects

Failure rate predictions for 0.35 /spl mu/m Flash EEPROM memories from accelerated read disturb tests

Impact of thermal overload operation on wirebond and metallization reliability in smart power devices

Reliability of embedded SONOS memories

Self-aligned access gate technology for compact embedded flash memories

Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing

Optimized cell structure for FinFET array Flash memory

Phase-change memory technology for embedded applications

Integration and cell characteristics for high density PRAM

Self-aligned recessed source/drain ultra-thin body SOI MOSFET technology

Off current adjustment in ultra-thin SOI MOSFETs

Flexible semiconductor devices: fingerprint sensor and electrophoretic display on plastic [TFT based]

Silicon oxide formation for TFTs using humid ozone-enriched gas ambient at low temperature

Determination of band-gap narrowing in heavily doped n-type GaAs and n-type GaInP from solar cell performance

Comparative analysis of basic transport properties in the inversion layer of bulk and SOI MOSFETs: a Monte-Carlo study

Interface passivation mechanisms in metal gated oxide capacitors

90nm RF CMOS technology for low-power 900MHz applications [amplifier example]

Requirements on CD and overlay for 200 GHz QSA SiGe:C HBTs

Influence of self heating in a BiCMOS on SOI technology

Monolithic CMOS detector module for photon counting and picosecond timing

Ge-on-Si pin-photodiodes for vertical and in-plane detection of 1300 to 1580 nm light

Universal integrated PIN photodetector

A micro-scale hot-surface device based on non-radiative carrier recombination [gas sensor example application]

Influence of an accumulation back-gate voltage on the low-frequency noise spectra of 0.13 /spl mu/m fully-depleted SOI MOSFETs fabricated on ELTRAN and UNIBOND wafers

Analysis of substrate noise propagation in a lightly doped substrate [mixed-signal ICs]

The 1/f noise versus sheet resistance in poly-Si is similar to poly-SiGe resistors and Au-layers

Advanced SEU engineering using a triple well architecture [CMOS SRAM]

Electrical characterization and modelling of high-performance SON DG MOSFETs

Device design for sub 90 nm MOSFETs for sample and hold circuits

High frequency characteristics of MOSFETs with compact waffle layout

Efficient simulation framework for circuit design with future device technologies [MOS structures]

Self-consistent characterization of gate controlled diodes for CMOS technology monitoring

Evaluation of strain-induced mobility variation in TiN metal gate SOI n-MOSFETs

Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology

TCAD modelling of PLAD implantations and application to sub-65nm technological nodes [plasma doping]

Investigation of charge transport in organic single crystals using a "flip-crystal" field-effect technique

Bias stress in pentacene transistors measured by four probe transistor structures

Organic thin film transistors: a DC model for circuit simulation

Gain and polaron absorption in electrically pumped single-layer organic laser diodes

Injection-limited current in a polymeric heterojunction

Improving the ambipolar behavior of Schottky barrier carbon nanotube field effect transistors

Negative differential conductance in silicon nanocrystal single-electron devices

Investigation of InP/InGaAs pnp /spl delta/-doped heterojunction bipolar transistor

Low voltage (1.2V) and high performance mobile DRAM device technology with dual poly-silicon gate using plasma nitrided gate oxide

Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

Analysis and application of energy capability characterization methods in power MOSFETs

The electro-thermal Smoothie database model for LDMOS devices

A new substrate current free nLIGBT for junction isolated technologies

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

32nd European Solid-State Device Research Conference

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Perspective of FinFETs for analog applications

Content Provider	IEEE Xplore Digital Library
Author	Kilchytska, V. Collaert, N. Rooyackers, R. Lederer, D. Raskin, J.-P. Flandre, D.
Copyright Year	2004
Description	Author affiliation: Microelectron. Lab., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium (Kilchytska, V.)
Abstract	FinFETs are known to be one of the most promising technological solutions to create high-performance ultra-scaled Si MOSFETs. In this paper, we present the first detailed experimental investigation of the analog performance of FinFETs with channel lengths down to 50 nm. We demonstrate that such devices have very strong potential for analog applications, mainly thanks to a super-high value of the Early voltage and hence intrinsic gain, which they can provide. The impact of fin width on device characteristics is also analysed. We show that the narrowest devices appear as the most promising, since they operate in the fully-depleted regime, even possibly in volume inversion.
Starting Page	65
Ending Page	68
File Size	292380
Page Count	4
File Format	PDF
ISBN	0780384784
DOI	10.1109/ESSDER.2004.1356489
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-23
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Microelectronics MOSFETs Voltage Laboratories Microwave technology Paper technology Transconductance Performance gain Degradation
Content Type	Text
Resource Type	Article

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