NDLI: Double gate silicon-on-insulator transistors: n/sup +/-n/sup +/ gate versus n/sup +/-p/sup +/ gate configuration

Content Provider	IEEE Xplore Digital Library
Author	Gamiz, F. Roldan, J.B. Godoy, A. Jimenez-Molinos, F.
Copyright Year	2004
Description	Author affiliation: Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain (Gamiz, F.; Roldan, J.B.; Godoy, A.; Jimenez-Molinos, F.)
Abstract	We have studied electron mobility behavior in asymmetric double-gate silicon on insulator (DGSOI) inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices. The electron mobility curves in asymmetric DGSOI devices are shown to be considerably below the mobility curves corresponding to symmetric devices, in the whole range of silicon thicknesses. We show that the lack of symmetry in the asymmetric DGSOI structure produces the loss of the volume inversion effect. In addition, we show that as the silicon thickness is reduced, the conduction effective mass of electrons in asymmetric devices is lower than that in the symmetric case, but that the greater confinement of electrons in the former case produces a stronger increase in the phonon scattering rate, and in the surface roughness scattering rate.
Starting Page	173
Ending Page	176
File Size	323954
Page Count	4
File Format	PDF
ISBN	0780384784
DOI	10.1109/ESSDER.2004.1356517
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-23
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon on insulator technology Threshold voltage Doping MOSFETs Electron mobility Scattering Semiconductor films Voltage control Effective mass Phonons
Content Type	Text
Resource Type	Article

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