NDLI: A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration

Content Provider	IEEE Xplore Digital Library
Author	U-Fat Chio Chi-Hang Chan Hou-Lon Choi Sai-Weng Sin Seng-Pan U. Martins, R.P.
Copyright Year	2011
Description	Author affiliation: State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China (U-Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U) \|\| On leave from Instituto Superior Técnico/TU of Lisbon, Portugal (Martins, R.P.)
Abstract	This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration techniques, uniform-sized dynamic comparators are employed to reduce the process-mismatch variation and nonlinearity error, when compared with the conventional structures. The ADC achieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s, with ERBW of 300MHz and 350MHz, respectively. The power consumption is 2.3mW only from 1.2-V supply at 300MS/s.
Starting Page	363
Ending Page	366
File Size	590699
Page Count	4
File Format	PDF
ISBN	9781457707032
ISSN	19308833
e-ISBN	9781457707049
e-ISBN	9781457707025
DOI	10.1109/ESSCIRC.2011.6044982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-12
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Noise Arrays Quantization Switches CMOS integrated circuits Capacitance
Content Type	Text
Resource Type	Article

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