NDLI: Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver

Content Provider	IEEE Xplore Digital Library
Author	Bakar, F.A. Nieminen, T. Nehal, Q. Ukkonen, P. Saari, V. Halonen, K.
Copyright Year	2011
Description	Author affiliation: Aalto University School of Electrical Engineering, SMARAD-2, Department of Micro- and Nanosciences, P.0 Box 11000, FIN-00076 Aalto, Finland (Bakar, F.A.; Nieminen, T.; Nehal, Q.; Ukkonen, P.; Saari, V.; Halonen, K.)
Abstract	An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying $1.6mm^{2}$ (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.
Starting Page	207
Ending Page	210
File Size	558789
Page Count	4
File Format	PDF
ISBN	9781457707032
ISSN	19308833
e-ISBN	9781457707049
e-ISBN	9781457707025
DOI	10.1109/ESSCIRC.2011.6044901
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-12
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband Gain Receivers Bandwidth Synthetic aperture radar Tuning Analog-digital conversion
Content Type	Text
Resource Type	Article

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