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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ashry, A. Aboushady, H. |
| Copyright Year | 2011 |
| Description | Author affiliation: LIP6 Laboratory, University of Pierre & Marie Curie, UPMC, Paris VI, France (Ashry, A.; Aboushady, H.) |
| Abstract | A $4^{th}$ order subsampled RF LC ∑Δ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2GHz and centered at 2.4GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitter but also for its more convenient frequency response to subsampled ∑Δ ADCs. An efficient algorithm for the tuning and calibration of the LC-based loop filter is presented. The ADC is implemented in a standard 130nm CMOS technology. It achieves a 51dB SFDR and a 40dB SNDR in a 25MHz BW and consumes only 19mW from a 1.2V supply. |
| Starting Page | 263 |
| Ending Page | 266 |
| File Size | 1074171 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457707032 |
| ISSN | 19308833 |
| e-ISBN | 9781457707049 |
| e-ISBN | 9781457707025 |
| DOI | 10.1109/ESSCIRC.2011.6044957 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-09-12 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Radio frequency CMOS integrated circuits Clocks Mixers CMOS technology Latches |
| Content Type | Text |
| Resource Type | Article |
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