NDLI: A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS

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Table of contents

2011 Symposium on VLSI Circuits - Conference Schedule

Session quick index

Session 1 - Welcome and plenary session I

The Hayabusa mission - Its seven years flight

The swarm at the edge of the cloud - A new perspective on wireless

Session 2 - Switching DC-DC converters

A 50.3ns transient-response CR-free SIMO power converter with adaptive current compensation

A 98% cross-talk self-cancellation single-inductor dual-output DC-DC converter using bidirectional power prediction (BPP) control in 65nm CMOS

A single-inductor 8-channel output DC-DC boost converter with time-limited one-shot current control and single shared hysteresis comparator

Fixed-frequency adaptive-on-time boost converter with fast transient response and light load efficiency enhancement by auto-frequency-hopping

A spurious-free switching buck converter using a delta-sigma modulation controller with a scalable sampling frequency

Session 3 - Advanced wireless transceivers

A 0.38THz fully integrated transceiver utilizing quadrature push-push circuitry

A 10Gb/s 45mW adaptive 60GHz baseband in 65nm CMOS

A 2.5GHz delay-based wideband OFDM outphasing modulator in 45nm-LP CMOS

A configurable multi-band multi-mode transmitter with spur cancellation through digital baseband

A $3.5mm^{2},$ inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates

Session 4 - Oversampling converters

A 12-ENOB 6X-OSR noise-shaped pipelined ADC utilizing a 9-bit linear front-end

A 32nm, 1.05V, BIST enabled, 10–40MHz, 11-9 bit, $0.13mm^{2}$ digitized integrator MASH ΔΣ ADC

A continuous-time, jitter insensitive ΣΔ modulator using a digitally linearized G-C integrator with embedded SC feedback DAC

A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS

A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator

Session 5 - Circuit and system integration

Measurement, analysis and improvement of supply noise in 3D ICs

Isolation techniques against substrate noise coupling utilizing through silicon via (TSV) for RF/mixed-signal SoCs

A fully-integrated cantilever-based DNA detection SoC in a CMOS Bio-MEMS process

A 65nm CMOS Movable Parts Manager for optical disc system

20-µW operation of an a-IGZO TFT-based RFID chip using purely NMOS “active” load logic gates with ultra-low-consumption power

Session 6 - High performance DACs and amplifiers

A 100dB DR ground-referenced single-ended Class-D amplifier in 65nm CMOS

A ping-pong-pang current-feedback instrumentation amplifier with 0.04% gain error

A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz f BiCMOS process

A 3GS/s, 9b, 1.2V single supply, pure binary DAC with >50dB SFDR up to 1.5GHz in 65nm CMOS

A 10b 600MS/s multi-mode CMOS DAC for multiple Nyquist zone operation

Session 7 - Embedded SRAM and applications

A 40nm fully functional SRAM with BL swing and WL pulse measurement scheme for eliminating a need for additional sensing tolerance margins

A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM with low-energy disturb mitigation scheme

A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms

A Chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST

Session 8 - Multi gigabit wireline communication

An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects

A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on

An 8Gb/s forwarded-clock I/O receiver with up to 1GHz constant jitter tracking bandwidth using a weak injection-locked oscillator in 0.13µm CMOS

A $0.12mm^{2}$ 5Gbps receiver with a level shifting equalizer and a cumulative-histogram-based adaptation engine

Session 9 - Image sensors

A digital CDS scheme on fully column-inline TDC architecture for an APS-C format CMOS image sensor

A 640×480 image sensor with unified pixel architecture for 2D/3D imaging in 0.11µm CMOS

A dual in-pixel memory CMOS image sensor for computation photography

A CMOS Σ-Δ photodetector array for bioluminescence-based DNA sequencing

Session 10 - Plenary session II

Circuit challenges for future computing systems

Smart devices and services in healthcare and wellness

Session 11- Fractional-N PLLs

A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 ps jitter

A −104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor

A 3.6GHz 1MHz-bandwidth ΔΣ fractional-N PLL with a quantization-noise shifting architecture in 0.18µm CMOS

A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC

Session 12 - Pipelined ADCs

A 12b 3GS/s pipeline ADC with 500mW and 0.4 $mm^{2}$ in 40nm digital CMOS

An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects

A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture

A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC

A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS

Session 13 - High speed digital for interconnects

The 10G-EPON OLT and ONU LSIs for the coexistence of 10G-EPON and GE-PON toward the next FTTH era

A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder

A 1.1 GOPS/mW FPGA chip with hierarchical interconnect fabric

SWIFT: A 2.1Tb/s 32×32 self-arbitrating manycore interconnect fabric

Session 14 - Bio interfaces

A configurable and low-power mixed signal SoC for portable ECG monitoring applications

A 96-channel full data rate direct neural interface in 0.13µm CMOS

BioBolt: A minimally-invasive neural interface for wireless epidural recording by intra-skin communication

A photovoltaic-driven and energy-autonomous CMOS implantable sensor

Session 15 - Clocking building blocks

A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS

553-GHz signal generation in CMOS using a quadruple-push oscillator

High-PSRR all-digital delay locked loop with burst update mode and power noise damping scheme

A programmable MEMS-based clock generator with sub-ps jitter performance

Session 16 - Ultra low power transceivers

A battery-less WiFi-BER modulated data transmitter with ambient radio-wave energy harvesting

315MHz energy-efficient injection-locked OOK transmitter and 8.4µW power-gated receiver front-end for wireless ad hoc network in 40nm CMOS

A 550µW inductorless bandpass quantizer in 65 nm CMOS for 1.4-to-3GHz digial RF receivers

A $1mm^{3}$ 2Mbps 330fJ/b transponder for implanted neural sensors

Session 17 - Bio sensors and applications

A 0.5-V sub-mW wireless magnetic tracking transponder for radiation therapy

A 256 channel magnetoresistive biosensor microarray for quantitative proteomics

Magnetic relaxation detector for microbead labels in biomedical assays

Low power control IC for efficient high-voltage piezoelectric driving in a flying robotic insect

Session 18 - High performance circuit techniques

A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines

$LC^{2}:$ Limited contention level converter for robust wide-range voltage conversion

Adaptive robustness tuning for high performance domino logic

A 381 fs/bit, 51.7 nW/bit nearest hamming-distance search circuit in 65 nm CMOS

Session 19 - Nonvolatile memories

A 21nm high performance 64Gb MLC NAND flash memory with 400MB/s asynchronous toggle DDR interface

A fast rewritable 90nm 512Mb NOR “B4-Flash” memory with 8F2 cell size

4-times faster rising V (10V), 15% lower power VPGM (20V), wide output voltage range voltage generator system for 4-times faster 3D-integrated solid-state drives

A 512Mb phase-change memory (PCM) in 90nm CMOS achieving 2b/cell

Session 20 - High speed and low power receiver techniques

A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS

A 40Gb/s adaptive receiver with linear equalizer and merged DFE/CDR

A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS

A 4.4uW wake-up receiver using ultrasound data communications

Session 21 - Device-based circuit techniques

A true random number generator using time-dependent dielectric breakdown

On-chip combined C-V/I-V transistor characterization system in 45-nm CMOS

Electrical monitoring of gate and active area mask misalignment error

A 80kS/s 36µW resistor-based temperature sensor using BGR-free SAR ADC with a unevenly-weighted resistor string in 0.18µm CMOS

PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability

Session 22 - DRAM and memory interfaces

3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype

In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise $4F^{2}$ DRAM array operable at 10-fF cell capacitance

A 12.8-Gb/s/link tri-modal single-ended memory interface for graphics applications

A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface

Session 23 - Power management for energy harvesting

Platform architecture for solar, thermal and vibration energy combining with MPPT and single inductor

A reconfigurable SITITO boost/buck regulator with sub-threshold cross-regulation-free dual-mode control for energy-harvesting applications

A battery-free 225 nW buck converter for wireless RF energy harvesting with dynamic on/off time and adaptive phase lead control

A fully-integrated system power aware LDO for energy harvesting applications

A 13.56MHz CMOS rectifier with switched-offset for reversion current control

Session 24 - Digital processors

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

A 75µW, 16-channel neural spike-sorting processor with unsupervised clustering

A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios

Fully integrated CMOS SoC for 3D Blu-ray player applications

A 52mW full HD 160-degree object viewpoint recognition SoC with visual vocabulary processor for wearable vision applications

Session 25 - Emerging ADCs

A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

A 1-V, 8b, 40MS/s, 113µW charge-recycling SAR ADC with a 14µW asynchronous controller

Digitally synthesized stochastic flash ADC using only standard digital cells

A reconfigurable 1GSps to 250MSps, 7-bit to 9-bit highly time-interleaved counter ADC in 0.13µm CMOS

A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Session 26 - Power management technique

Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500ps, and 85mV dropout voltage

MEMS-switch-based power management with zero-power voltage monitoring for energy accumulation architecture on dust-size wireless sensor nodes

A 210 nW 29.3 ppm/°C 0.7 V voltage reference with a temperature range of −50 to 130 °C in 0.13 µm CMOS

A voltage-reference-free pulse density modulation (VRF-PDM) 1-V input switched-capacitor 1/2 voltage converter with output voltage trimming by hot carrier injection and periodic activation scheme

A fast-transient DVS-capable switching converter with ΔI-emulated hysteretic control

Session 27 - Signal processing for wireline

A laser ranging radar transceiver with modulated evaluation clock in 65nm CMOS technology

10Gb/s serial I/O receiver based on variable reference ADC

10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS

A direct sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

Session 28 - Nonvolatile memory applications

A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance

Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control

A content addressable memory using magnetic domain wall motion cells

A non-volatile look-up table design using PCM (phase-change memory) cells

Special session - Technology highlights

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and $0.08µm^{2}$ SRAM cell

Comprehensive SRAM design methodology for RTN reliability

Unified understanding of V and I variability in tri-gate nanowire MOSFETs

1mA/um-I strained SiGe-IFQW pFETs with raised and embedded S/D

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A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Yung-Hui Chung Jieh-Tsorng Wu
Copyright Year	2011
Description	Author affiliation: Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan (Yung-Hui Chung; Jieh-Tsorng Wu)
Abstract	An 8-bit subranging ADC was fabricated using a 55nm CMOS technology. To enhance speed, subranging is executed by activating comparators in the digital domain. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from a 1.2V supply. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR are 55dB and 43.5dB respectively. The ADC occupies an active area of $0.2mm^{2}.$ Its FOM is 125fJ/conversion-step.
Starting Page	128
Ending Page	129
File Size	933633
Page Count	2
File Format	PDF
ISBN	9781612841755
ISSN	21585636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-15
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP (Japan Society of Applied Physi
Subject Keyword	Latches Calibration Semiconductor device measurement Very large scale integration CMOS technology Capacitors CMOS integrated circuits calibration Analog-digital conversion subranging ADC comparators (circuits)
Content Type	Text
Resource Type	Article

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