NDLI: A 2.5Gb/s ATM Label Translator Implemented by Using GaAs Technology

Content Provider	IEEE Xplore Digital Library
Author	Moussa, I. Lassen, P. S. Torki, K.
Copyright Year	1996
Description	Author affiliation: TIMA lab., 46 Av. Felix Viallet 38031 Grenoble FRANCE. moussa@verdon.imag.fr (Moussa, I.) \|\| CMP, 46 Av. Felix Viallet 38031 Grenoble FRANCE (Torki, K.) \|\| CBT, Technical University of Denmark, DENMARK; Vitesse Semiconductor, CA USA (Lassen, P. S.)
Abstract	Routing tables for communication networks can be designed using several approaches, including table look-up, Content-Addressable Memory (CAM), hashing, and tries. This paper presents a GaAs VLSI implementation of an efficient table lookup algorithm for 2.5 Gb/s ATM switching systems. This algorithm presents some very promising features such as the number of Virtual Channels which can reach 30.000 possible connections. An extra header of three bytes is attached to the cell header which contains policing and priorities information for use inside the switch. Routing information is performed by using the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) in the incoming cell to access the header translation table. The VLSI chip is fabricated using 0.6 ¿m gate GaAs MESFETs, by VITESSE Semiconductor and it is housed in a 132 pin LDCC package. The Lable Translator chip is expected to operate at 312Mhz with an associated power dissipation of 4W.
Starting Page	292
Ending Page	295
File Size	1795311
Page Count	4
File Format	PDF
ISBN	2863321978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-17
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Editions Frontiers
Subject Keyword	Gallium arsenide Asynchronous transfer mode Routing Very large scale integration Switches Communication networks Computer aided manufacturing CADCAM Table lookup Switching systems ATM Switch Gallium Arsenide Design Technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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