NDLI: A Punctured Viterbi Decoder Compatible with DVB Standards

Content Provider	IEEE Xplore Digital Library
Author	Deltoso, C. Cand, M. Sponga, L.
Copyright Year	1996
Description	Author affiliation: France Telecom - CNET - 28, Chemin du Vieux Chêne, 38243 MEYLAN Cédex - FRANCE. (Cand, M.; Sponga, L.) \|\| France Telecom - CNET - 28, Chemin du Vieux Chêne, 38243 MEYLAN Cédex - FRANCE. e-mail: deltoso@cns.cnet.fr (Deltoso, C.)
Abstract	This paper presents an example of a Viterbi decoder compatible with DVB standards. The chosen architecture implements the Register Exchange Algorithm (REA). The REA has often been considered to be a more complex architectural solution than its competitor the Trace Back Algorithm (TBA). This paper aims at demonstrating that VLSI implementations of the Viterbi Algorithm are feasible using REA without great an increase in complexity compared to TBA. The chip designed in a 0.5 ¿m CMOS technology from SGS-Thomson, has been entirely synthesized from generic VHDL models. The area is almost 10 $mm^{2}$ for the core and 20 $mm^{2}$ for the chip with pads. The maximum throughput is about 70 Mbits/s.
Starting Page	368
Ending Page	371
File Size	1231365
Page Count	4
File Format	PDF
ISBN	2863321978
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-17
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Editions Frontiers
Subject Keyword	Viterbi algorithm Digital video broadcasting Maximum likelihood decoding Clocks Forward error correction Telecommunication standards CMOS technology Convolutional codes Additive white noise Gaussian noise
Content Type	Text
Resource Type	Article

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