NDLI: Pushing CMOS beyond the roadmap

Content Provider	IEEE Xplore Digital Library
Author	Risch, L.
Copyright Year	2005
Description	Author affiliation: Corporate Res., Infineon Technol., Munich, Germany (Risch, L.)
Abstract	Today, the 90nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, wafer bonded double gate and SON gate all around have been demonstrated with good electrical characteristics at gate lengths of 25-10nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2nm gate length. Multi-gate transistors have also been implemented in high density flash memory cells down to 20nm. Large Vt shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.
Starting Page	63
Ending Page	68
File Size	1205746
Page Count	6
File Format	PDF
ISBN	0780392051
DOI	10.1109/ESSCIR.2005.1541558
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-12
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Silicon Production Electrostatics FinFETs Wafer bonding Electric variables Quantum mechanics Predictive models Flash memory cells
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Pushing CMOS beyond the roadmap

A comprehensive study of single-electron effects in multiple-gate MOSFETs

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

Nanoscale Si-based 3-dimensional MOSFETs

A Quantum-Mechanical Analysis of the Electrostatics in Multiple-Gate FETs

A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

A new approach to the self-consistent solution of the Schrodinger-Poisson equations in nanowire MOSFETs

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

Nonvolatile Flash Memories in Silicon-on-sapphire CMOS

Pushing CMOS beyond the roadmap

Similar Documents

Pushing CMOS beyond the roadmap

A comprehensive study of single-electron effects in multiple-gate MOSFETs

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

Nanoscale Si-based 3-dimensional MOSFETs

A Quantum-Mechanical Analysis of the Electrostatics in Multiple-Gate FETs

A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

A new approach to the self-consistent solution of the Schrodinger-Poisson equations in nanowire MOSFETs

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

Nonvolatile Flash Memories in Silicon-on-sapphire CMOS

Pushing CMOS beyond the roadmap