NDLI: A 35nW/pixel 2D visual motion sensor

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"Silicon forever! Really?"

Future devices for information processing

Terahertz technology: devices and applications

Silicon nano-photonics: where the photons meet the electrons

Towards a molecule - computer? Resources and technologies to compute within a single molecule

Engineering wafers for the nanotechnology era

Digital control of RF power amplifiers for next-generation wireless communications

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Notice of Violation of IEEE Publication Principles A 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop

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Dynamic state-retention flip flop for fine-grained sleep-transistor scheme

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Multistandard carrier generation system for quad-band GSM/WCDMA (FDD-TDD)/WLAN (802.11 a-b-g) radio

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A 3.33Gb/s (1200,720) low-density parity check code decoder

ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs

ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB

A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch

A cellular-band CDMA 0.25/spl mu/m CMOS LNA linearized using active post-distortion

IP2 calibrator using common mode feedback circuitry

A modified LMS adaptive filter architecture with improved stability at RF

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CAFFEINE: template-free symbolic model generation of analog circuits via canonical form functions and genetic programming

A 0.6V 100dB 5.2MHz transconductance amplifier realized in a multi-V/sub T/ process

120nm CMOS OPAMP with 690 MHz f/sub T/ and 128 dB DC gain

A 1 watt audio amplifier in a standard digital 90-nm CMOS technology

100-MS/s 14-b track-and-hold amplifier in 0.18-/spl mu/m CMOS

A low-power, 10GS/s track-and-hold amplifier in SiGe BiCMOS technology

A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator

Single-chip CMOS pulse generator for UWB systems

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A 5.1-/spl mu/W UHF RFID tag chip integrated with sensors for wireless environmental monitoring

A high accurate logarithmic amplifier system with wide input range and extreme low temperature coefficient

A BiCMOS ultrasound front end signal processor for high temperature applications

Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components

An on-chip multi-channel waveform monitor for mixed-signal VLSI diagnostics

Memory testing improvements through different stress conditions

A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology

Silicon bipolar circuits for wideband FM CATV transmission

SOI four-gate transistors (G/sup 4/-FETs) for high voltage analog applications

A 1.2V-21dBm OIP3 4/sup th/-order active-g/sub m/-RC reconfigurable (UMTS/WLAN) filter with on-chip tuning designed with an automatic tool

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Ultra low-power analog Morlet wavelet filter in 0.18 /spl mu/m BiCMOS technology

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A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

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Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO

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Physical random number generators for cryptographic application in mobile devices

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A 75dB image rejection IF-input quadrature sampling SC /spl Sigma//spl Delta/ modulator

An audio FIR-DAC in a BCD process for high power class-D amplifiers

Scalable circuits for supply noise measurement

Autonomous di/dt noise control scheme for margin aware operation

A built-in I/sub DDQ/ testing circuit

Optimally-placed twists in global on-chip differential interconnects

Analysis of low noise three-phase asynchronous data transmission

Differential image sensor with high common mode rejection

A single-photon-avalanche-diode 3D imager

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A novel current-mode very low power analog CMOS four quadrant multiplier

A novel four-quadrant analog multiplier using SOI four-gate transistors (G/sup 4/-FETs)

A 1 V, 26 /spl mu/W extended temperature range band-gap reference in 130-nm CMOS technology

A low-power 2-GSample/s comparator in 120 nm CMOS technology

Variable gain amplifier in polar loop modulation transmitter for EDGE

WCDMA multicarrier receiver for base-station applications

Fully-integrated WCDMA SiGeC BiCMOS transceiver

A 10BIT 30MSPS CMOS A/D converter for high performance video applications

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A 35nW/pixel 2D visual motion sensor

Content Provider	IEEE Xplore Digital Library
Author	Guangbin Zhang Hoi Lee Jin Liu
Copyright Year	2005
Description	Author affiliation: Texas Univ., Richardson, TX, USA (Guangbin Zhang; Hoi Lee; Jin Liu)
Abstract	An ultra-low power visual motion sensor based on the time stamped pixel structure is presented in this paper. Both the current-clamping circuits in the edge detector and the static logic circuit in the time stamp component are developed to allow the pixel dissipating tens of nanowatt power. In addition, both proposed edge detector and time stamp component reduce the pixel size simultaneously. Implemented in a CMOS 0.35/spl mu/m process, a 2D vision motion sensor of 32/spl times/32 arrays only consumes 35nW/pixel with the chip area of (40/spl mu/m/spl times/40/spl mu/m)/pixel.
Starting Page	419
Ending Page	422
File Size	373537
Page Count	4
File Format	PDF
ISBN	0780392051
DOI	10.1109/ESSCIR.2005.1541649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-12
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sensor arrays Detectors Energy consumption Intelligent sensors Logic circuits Motion analysis Smart pixels Motion detection Voltage CMOS process
Content Type	Text
Resource Type	Article

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