NDLI: High performance pipelining method for static circuits using heterogeneous pipelining elements

Content Provider	IEEE Xplore Digital Library
Author	Garg, M.
Copyright Year	2003
Description	Author affiliation: Philips Res. Labs., Eindhoven, Netherlands (Garg, M.)
Abstract	A high performance pipelining method for static circuits is investigated using heterogeneous pipelining elements. This method selectively uses pulse flip-flops and master-slave flip-flops in the pipeline to optimize speed, power and robustness. Critical paths in the pipeline logic are terminated by pulse flip-flops to make them skew tolerant and to allow them to steal time from the next pipeline stage. Non-critical fast paths are terminated by master-slave flip-flops to keep their advantages of smaller area and power, and better robustness. Thus this method exploits best of MS flip-flops and pulse flip-flops to improve overall design cost and performance. We implemented a DSP using this methodology for analysis, which shows a reduction in the pipelining overhead by a factor of 3 at the cost of 7% increase in the area. We show that this method is fully compatible with the flip-flop based CAD flow making it useful for both processors as well as high performance ASICs.
Sponsorship	IEEE SSCS Infieon Technol. ATMEL Tower Semiconductor LTD
Starting Page	185
Ending Page	188
File Size	427284
Page Count	4
File Format	PDF
ISBN	0780379950
DOI	10.1109/ESSCIRC.2003.1257103
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-16
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Circuits Flip-flops Master-slave Robustness Costs Optimization methods Logic Digital signal processing Design automation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in