NDLI: A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS

Content Provider	IEEE Xplore Digital Library
Author	Kim, D.D. Jonghae Kim Choongyeun Cho
Copyright Year	2008
Description	Author affiliation: IBM, Hopewell Junction, NY (Kim, D.D.; Jonghae Kim; Choongyeun Cho)
Abstract	As an essential clock-system component, millimeter-wave dividers have been implemented for V- and W-band channels. This has also served as a standard benchmark vehicle that reveals high-speed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled, and they are comparable to dividers in other technologies. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the $f_{div}$ $_{,}$ $_{max},$ the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the $f_{div}$ $_{,}$ $_{max},$ since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.
Starting Page	460
Ending Page	628
File Size	654157
Page Count	169
File Format	PDF
ISBN	9781424420100
DOI	10.1109/ISSCC.2008.4523256
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-02-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hysteresis CMOS technology Performance evaluation Frequency conversion Tunable circuits and devices Clocks Millimeter wave technology Vehicles Circuit synthesis Frequency measurement
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wideband mmWave CML static divider in 65nm SOI CMOS technology

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

Scalable statistical measurement and estimation of a mmWave CML static divider sensitivity in 65nm SOI CMOS

Performance Variations of a 66GHz Static CML Divider in 90nm CMOS

A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOS

A 1.2V 15.6mW 81GHz 2:1 Static CML Frequency Divider with a Band-Pass Load in a 90nm SOI CMOS Technology

A Millimeter-Wave 90-nm CMOS Self-Mixing Frequency Divider

A complementary injection technique for performance enhancing of CML dividers

A 44 GHz 0.18μm CMOS Superharmonic Frequency Divider

A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS

Similar Documents

Wideband mmWave CML static divider in 65nm SOI CMOS technology

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

Scalable statistical measurement and estimation of a mmWave CML static divider sensitivity in 65nm SOI CMOS

Performance Variations of a 66GHz Static CML Divider in 90nm CMOS

A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOS

A 1.2V 15.6mW 81GHz 2:1 Static CML Frequency Divider with a Band-Pass Load in a 90nm SOI CMOS Technology

A Millimeter-Wave 90-nm CMOS Self-Mixing Frequency Divider

A complementary injection technique for performance enhancing of CML dividers

A 44 GHz 0.18μm CMOS Superharmonic Frequency Divider

A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS