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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Noguchi, H. Yoshida, N. Uchida, H. Ozaki, M. Kanemitsu, S. Wada, S. |
| Copyright Year | 2008 |
| Description | Author affiliation: NEC, Kawasaki (Noguchi, H.; Yoshida, N.) |
| Abstract | In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. The CDR circuit is fabricated using a 0.18 mum SiGe BiCMOS process. The $f_{t}$ and $f_{max}$ are 200 GHz and 180 GHz, respectively. To overcome a severe degradation of BER performance due to this misalignment, a 40 Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor feedback is developed. The key approaches are 40 Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, an adaptive decision-point control (ADPC) scheme by using the EOM feedback, a decision- point adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation. |
| Starting Page | 228 |
| Ending Page | 609 |
| File Size | 586079 |
| Page Count | 382 |
| File Format | |
| ISBN | 9781424420100 |
| DOI | 10.1109/ISSCC.2008.4523140 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-02-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Programmable control Adaptive control Bit error rate Feedback circuits Monitoring Phase detection Signal analysis Silicon germanium Germanium silicon alloys BiCMOS integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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