NDLI: An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Content Provider	IEEE Xplore Digital Library
Author	Giannini, V. Nuzzo, P. Chironi, V. Baschirotto, A. Van der Plas, G. Craninckx, J.
Copyright Year	2008
Description	Author affiliation: lMEC, Leuven (Giannini, V.; Nuzzo, P.)
Abstract	Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.
Starting Page	238
Ending Page	610
File Size	697133
Page Count	373
File Format	PDF
ISBN	9781424420100
DOI	10.1109/ISSCC.2008.4523145
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-02-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction Frequency conversion Sampling methods Phased arrays Solid state circuits Calibration Switches Phase noise Adders Energy consumption
Content Type	Text
Resource Type	Article

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