NDLI: A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Mazzanti, A. Sosio, M. Repossi, M. Svelto, F.
Copyright Year	2008
Description	Author affiliation: Univ. of Modena & Reggio Emilia, Modena (Mazzanti, A.)
Abstract	Performance of standard CMOS implementations has proved sufficient up to 60 GHz range and examples of operating blocks even beyond 60 GHz have been presented. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. The authors have proposed a half-harmonic 24 GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65 nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1 $mm^{2})$ low-power (below 100 mW) solution in an ultra- scaled RF CMOS process.
Starting Page	216
Ending Page	608
File Size	902417
Page Count	393
File Format	PDF
ISBN	9781424420100
DOI	10.1109/ISSCC.2008.4523134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-02-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency conversion Baseband Capacitors Voltage-controlled oscillators Frequency synthesizers Phase noise Transconductors Mixers Radiofrequency amplifiers Radio frequency
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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