NDLI: Ultra low power 2-tier 3D stacked sub-threshold H.264 intra frame encoder

Content Provider	IEEE Xplore Digital Library
Author	Samal, S.K. Kiyoung Kim Youngchan Kim Taesung Kim Hyuk-Jae Lee Taewhan Kim Sung Kyu Lim
Copyright Year	2013
Description	Author affiliation: Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA (Samal, S.K.; Sung Kyu Lim) \|\| Sch. of ECE, Seoul Nat. Univ., Seoul, South Korea (Kiyoung Kim; Youngchan Kim; Taesung Kim; Hyuk-Jae Lee; Taewhan Kim)
Abstract	Digital circuits used in sensor networks require longer battery life and do not demand a fast frequency of operation. Sub-threshold circuits for such applications are an attractive option. Three dimensional ICs (3DICs) on the other hand is an emerging technology which helps in miniaturization and reduction in interconnects, resulting in power saving and performance improvement. Several works on sub-threshold circuits and TSV based 3DICs have been studied independently but none have studied the impact of 3D stacking of sub-threshold circuits. We design and study an ultra-low power 2-tier 3D sub-threshold implementation of H.264 intra frame encoder that encodes video frames. The encoder consumes 0.73μW power at 16.13 KHz clock frequency for a typical application of encoding a Common Image Format (CIF) frame. The motivation is to assess the feasibility of the use of extreme low power video encoders in image sensor based sensor networks. Low power operation is highly beneficial to such unattended sensor networks by extending their battery life. Sub-threshold design helps us in this respect while 3D stacking minimizes footprint area, helps in off-chip to on-chip memory integration and improves timing performance.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	1
Ending Page	2
File Size	2232497
Page Count	2
File Format	PDF
ISBN	9781479913619
DOI	10.1109/S3S.2013.6716532
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Stacking Standards Layout Low-power electronics Timing Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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