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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mori, T. Ida, J. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr. & Electron. Eng., Kanazawa Inst. of Technol., Kanazawa, Japan (Mori, T.; Ida, J.) |
| Abstract | Ultra Low Power (ULP) LSI's require the steep subthreshold slope (SS) MOSFET. However, the theoretical SS limit of the conventional MOSFET is 60mV/dec at the room temperature. Recently, devices which have the less than 60mV/dec SS, such as the Tunnel FET (TFET) and the Impact Ionization MOS (I-MOS), have been studied. In addition to those, the steep SS MOSFET's using the Floating-Body (FB) SOI have been proposed. In this work, we report our finding of the FB and the Body-Tied (BT) SOI MOSFET with the super steep SS (<; 1mV/Dec) characteristics with the 0.15um SOI. We also discuss the possibility of it as a switching device for the ultra low voltage application, where we consider that the three points are the issues to improve; reducing the operation voltage, increasing Ion/Ioff ratios which also pay attention keeping the low Ioff, controlling hysteresis characteristics. |
| Sponsorship | IEEE Electron Devices Soc. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 1011413 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479913619 |
| DOI | 10.1109/S3S.2013.6716550 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Hysteresis MOSFET Voltage control Low voltage |
| Content Type | Text |
| Resource Type | Article |
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