NDLI: Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding

Content Provider	IEEE Xplore Digital Library
Author	Goto, M. Hagiwara, K. Iguchi, Y. Ohtake, H. Saraya, T. Higurashi, E. Toshiyoshi, H. Hiramoto, T.
Copyright Year	2013
Description	Author affiliation: Univ. of Tokyo, Tokyo, Japan (Saraya, T.; Higurashi, E.; Toshiyoshi, H.; Hiramoto, T.) \|\| NHK Sci. & Technol. Res. Labs., Tokyo, Japan (Goto, M.; Hagiwara, K.; Iguchi, Y.; Ohtake, H.)
Abstract	We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of $Au/SiO_{2}$ at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	1
Ending Page	2
File Size	604015
Page Count	2
File Format	PDF
ISBN	9781479913619
DOI	10.1109/S3S.2013.6716519
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Gold Bonding Electrodes CMOS integrated circuits Inverters Integrated circuit interconnections
Content Type	Text
Resource Type	Article

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Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding