NDLI: An SOI floating body charge monitor technique

Content Provider	IEEE Xplore Digital Library
Author	Saccamango, M.J. Kuang, J.B. Hsu, L.L. Ratanaphanyarat, S.
Copyright Year	1999
Description	Author affiliation: Enterprise Syst. Group, IBM Corp., Hopewell Junction, NY, USA (Saccamango, M.J.)
Abstract	SOI pass transistor circuits are vulnerable to initial-cycle parasitic bipolar current which can cause speed degradation or functional failures (Kuang et al, 1997; Lu et al, 1997). This paper describes a novel floating body charge monitoring method which effectively reduces the sensitivity of transient response in the initial cycles and improves circuit robustness and noise margin without using body-contacted devices. In doing so, we avoid the area penalty, issues of contact resistance, and modeling difficulties associated with body contacts. The charge monitor mimics the circuit configuration and biasing characteristics of a particular circuit, such as the MUX topology, which is prone to bipolar current-induced initial-cycle slowdown. When excess body charge is detected by the monitor circuit, an additional discharge path is automatically enabled to provide more switching current and thus minimize timing variation.
Starting Page	88
Ending Page	89
File Size	152601
Page Count	2
File Format	PDF
ISBN	0780363892
ISSN	1078621X
DOI	10.1109/SOI.2000.892783
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Condition monitoring Bipolar transistor circuits Degradation Transient response Noise robustness Noise reduction Circuit noise Contact resistance Circuit topology Computerized monitoring
Content Type	Text
Resource Type	Article

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