NDLI: A 1.1 V SOI CMOS frequency divider using body-inputting SCL circuit technology

Content Provider	IEEE Xplore Digital Library
Author	Fuse, T. Tokumasu, M. Kawanaka, S. Fujii, H. Kameyama, A. Yoshimi, M. Watanabe, S.
Copyright Year	1999
Description	Author affiliation: Lab. for Comput. & Network Syst., Toshiba Corp., Kawasaki, Japan (Fuse, T.)
Abstract	SOI CMOS technology is one of the most effective candidates for realization of low power and high performance digital/RF circuits, with demand for single-chip LSI in portable communications equipment. By optimizing the threshold voltage, the CMOS logic in digital circuits can operate at less than 1 V (Fujii et al, 1999; Fuse et al, 1997). In the series gating ECL (emitter coupled logic) or SCL (source coupled logic) which is often used in RF circuits, on the other hand, the minimum operating voltage is raised to 1.8-2.6 V, due to the stacked configuration where plural transistors are connected in series (Yamashina et al., 1992). In this paper, we propose a body-inputting SCL circuit, which decreases the minimum operating voltage to around 1 V, by applying the input signal to the body of SOI devices. The fabricated 1/128 frequency divider realized 1.1 V operation with a maximum clock frequency of 450 MHz and each current source of 35 /spl mu/A.
Starting Page	106
Ending Page	107
File Size	165568
Page Count	2
File Format	PDF
ISBN	0780363892
ISSN	1078621X
DOI	10.1109/SOI.2000.892792
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency conversion CMOS logic circuits CMOS digital integrated circuits CMOS technology Radio frequency Coupling circuits Logic circuits Voltage Large scale integration Communication equipment
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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