NDLI: A design procedure of predictive RF MOSFET model for compatibility with ITRS

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Session quick index

MPL session: Keynote/plenary session

MA3 session: SoC power optimization techniques

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors

Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation

A run-time distributed cooperative approach to optimize power consumption in MPSoCs

MB3 session: Analog 1

Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks

A digitally self-calibrated low-noise 7-bit folding A/D converter

A high-resolution and fast-conversion readout circuit for differential capacitive sensors

Jitter transfer function model and VLSI jitter filter circuits

MT1 session: Embedded tutorial

A holistic view on low power design

MA4 session: Low power SoC circuits

A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step

High speed recursion-free CORDIC architecture

A 1 ppm/°C bandgap voltage reference with new second-order Taylor curvature compensation

MB4 session: Analog 2

Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster

A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS

A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2

MT2 session: Embedded tutorial

Low-power SOC implementation: What you need to know

TA1 session: Multimedia processing

System-level exploration of mesh-based NoC architectures for multimedia applications

A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor

A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras

Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations

TB1 Session: System level design methodologies

Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming

Unleash the parallelism of 3DIC partitioning on GPGPU

Routability-driven RDL routing with pin reassignment

Statistical electro-thermal analysis with high compatibility of leakage power models

TA2 session: Design

Variation-tolerant design of D-flipflops

High speed and low power transceiver design with CNFET and CNT bundle interconnect

NBTI-aware statistical timing analysis framework

Implementation of a hardware-efficient EEG processor for brain monitoring systems

Design and analysis of an advanced static blocked multithreading architecture

TB2 session: System level design methodologies

A Folding Strategy for SAT solvers based on Shannon's expansion theorem

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures

Expandable MDC-based FFT architecture and its generator for high-performance applications

A SystemCAMS extension for the simulation of non-linear circuits

An automated control code generation approach for the SegBus platform

Luncheon speaker

TA3 session: Low power design

Power noise suppression technique using active decoupling capacitor for TSV 3D integration

Estimation of maximum application-level power supply noise

Simultaneous voltage island generation and floorplanning

Footer voltage feedforward domino technique for wide fan-in dynamic logic

Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits

Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs

TB3 session: Reconfigurable systems

Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation

Binary object recognition system on FPGA with bSOM

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array

Design of a link-controller architecture for multiple serial link protocols

High-Performance random data lookup for network processing

A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier

A CMOS low-power low-offset and high-speed fully dynamic latched comparator

A CMOS 6 bit 250MS/s A/D converter with input voltage range detectors

Clock buffer with duty cycle corrector

A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOS

8Gbps high-speed I/O transmitter with scalable speed, swing and equalization levels

Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration

A multi-channel frequency detection and monitoring system

Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness

Interconnect system compression analysis for multi-core architectures

Fan-in sensitive low power dynamic circuits performance statistical characterization

Energy efficient computation with self-adaptive single-ended body bias

Power minimization methodology for VCTL topologies

Hybrid MOSFET/CNFET based power gating structure

Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies

A BDD-based approach to design power-aware on-line detectors for digital circuits

An efficient VLSI architecture for extended variable block sizes motion estimation

A multimedia content generation methodology in support to SOC decoder development and validation

Effect of a polywell leometry on a CMOS photodiode array

MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoC

A method for efficient NoC test scheduling using deterministic routing

Flow oriented routing for NOCS

A globally-interconnected modular CMP system with communication on the fly

Energy and delay-aware mapping for real-time digital processing system on network on chip platforms

Thermal modelling of 3D multicore systems in a flip-chip package

Efficient multicasting scheme for irregular mesh-based NoCs

Towards formal system-level verification of security requirements during hardware/software codesign

Thermal via planning for temperature reduction in 3D ICs

A design procedure of predictive RF MOSFET model for compatibility with ITRS

WPL session: Plenary session

Plenary speaker

WA1 session: Embedded memory and systems 1

A novel architectural approach for control architectures in RF transceivers

A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receivers

A novel architecture for discrete chaotic signal generators

WT1 session: Embedded tutorial

Quality-driven SoC architecture synthesis for embedded applications

WA2 session: Network on chip 1

DyML: Dynamic Multi-Level flow control for Networks on Chip

A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip

Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC

WB2 session: Communication circuits and systems

A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme

Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory

Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder

WA3 session: Network on chip 2

Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip

Comparative performance evaluation of wireless and optical NoC architectures

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing

Power analysis for Asynchronous CLICHÉ Network-on-Chip

WB3 session: Embedded memory and systems 2

Way-load balancing scheme for mobile cache LRU replacement

Exploiting large on-chip memory space through data recomputation

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation

2009 IEEE International SOC Conference (SOCC)

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IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.

A design procedure of predictive RF MOSFET model for compatibility with ITRS

Content Provider	IEEE Xplore Digital Library
Author	SinNyoung Kim Tsuchiya, A. Onodera, H.
Copyright Year	2010
Description	Author affiliation: Dept. Communications and Computer Engineering, Kyoto University, 606-8501, JAPAN (SinNyoung Kim; Tsuchiya, A.; Onodera, H.)
Abstract	A design procedure for generating predictive MOS-FET models is proposed. Due to evolving nature of future prediction, predictive models based on a certain prediction soon become absolute. We have therefore developed a design procedure for maintaining compatibility with most up-to-date prediction such as ITRS. The design procedure can generate predictive RF models for the first time. Details of the design procedure for BSIM4 as a core model are explained, with an application to LNA design example.
Starting Page	396
Ending Page	399
File Size	2366048
Page Count	4
File Format	PDF
ISBN	9781424466825
e-ISBN	9781424466832
DOI	10.1109/SOCC.2010.5784704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Predictive models Radio frequency Mathematical model Resistance Integrated circuit modeling Capacitance
Content Type	Text
Resource Type	Article

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