NDLI: GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design

Content Provider	IEEE Xplore Digital Library
Author	Song Zhao Shaoping Tang Nandakumar, M. Scott, D.B. Sridhar, S. Chatterjee, A. Youngmin Kim Shyh-Horng Yang Shi-Charng Ai Ashburn, S.P.
Copyright Year	2002
Description	Author affiliation: SiTD, Texas Inst. Inc., MS, USA (Song Zhao; Shaoping Tang; Nandakumar, M.; Scott, D.B.; Sridhar, S.; Chatterjee, A.; Youngmin Kim; Shyh-Horng Yang; Shi-Charng Ai; Ashburn, S.P.)
Abstract	In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in process optimization for our 0.13 /spl mu/m/1.5 V low power (LP) CMOS transistors. We demonstrate that such predictive TCAD simulations to determine and optimize process conditions can effectively reduce development time and cost. We describe GIDL mechanisms in our 0.13 /spl mu/m/1.5 V LP transistors, and explain, via simulations, that the measured GIDL current manifests different IN behaviors depending on whether the dominant BTBT location is at the gate oxide/Si interface or below in the Si bulk.
Sponsorship	Japan Soc. Appl. Phys. IEEE Electron Devices Soc. IEICE IEEE EDS Japan Chapter IEEE EDS Kansai Chapter
Starting Page	43
Ending Page	46
File Size	229757
Page Count	4
File Format	PDF
ISBN	4891140275
DOI	10.1109/SISPAD.2002.1034512
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-04
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Japan Soc. of Applied Physics
Subject Keyword	Design optimization Tunneling Space exploration CMOS process Medical simulation MOS devices Power measurement Predictive models Cost function Current measurement
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 0.13-/spl mu/m, 0.78-/spl mu/m/sup 2/ low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-/spl mu/m CMOS technology

A device design study of 0.25 /spl mu/m gate length CMOS for 1 V low power applications

Radiation characterization of a low power 0.5 /spl mu/m SOI-CMOS technology

A high performance 0.13 /spl mu/m CMOS process for GHz microprocessor manufacture

New Transistor Structure Optimization for 0.25/spl mu/m Cmos Technology

High linearity performance of 0.13 /spl mu/m CMOS devices using field-plate technology

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design

Similar Documents

A 0.13-/spl mu/m, 0.78-/spl mu/m/sup 2/ low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-/spl mu/m CMOS technology

A device design study of 0.25 /spl mu/m gate length CMOS for 1 V low power applications

Radiation characterization of a low power 0.5 /spl mu/m SOI-CMOS technology

A high performance 0.13 /spl mu/m CMOS process for GHz microprocessor manufacture

New Transistor Structure Optimization for 0.25/spl mu/m Cmos Technology

High linearity performance of 0.13 /spl mu/m CMOS devices using field-plate technology

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design