NDLI: A strategy for enabling predictive TCAD in development of sub-100nm CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	Machala, C.F. Chakravarthi, S. Li, D. Yang, S.-H. Bowen, C.
Copyright Year	2002
Description	Author affiliation: Texas Instrum. Inc., Dallas, TX, USA (Machala, C.F.; Chakravarthi, S.)
Abstract	CMOS technology development is an expensive undertaking. Predictive TCAD can be a key tool in reducing the time and cost of CMOS development by acting as a virtual wafer fah where experimental lots are first simulated and the results analyzed before the first process step is ever run. In this way errors may be uncovered, poor splits eliminated and inadequate experimental designs improved. Each lot yields more information through better design and less waste. However, in order to achieve these improvements TCAD simulators must be quickly calibrated with new models that simulate the new physics for sub-100nm technology nodes. Because of the rapid pace of CMOS development, the available commercial simulators do not usually contain all the models needed in order to be predictive. This paper describes our efforts in upgrading the commercially available simulators TSUPREM4 and Dessis for the purpose of aiding in the development of sub-100nm high performance and low stand-by power CMOS technologies.
Sponsorship	Japan Soc. Appl. Phys. IEEE Electron Devices Soc. IEICE IEEE EDS Japan Chapter IEEE EDS Kansai Chapter
Starting Page	33
Ending Page	38
File Size	322764
Page Count	6
File Format	PDF
ISBN	4891140275
DOI	10.1109/SISPAD.2002.1034510
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-04
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Japan Soc. of Applied Physics
Subject Keyword	CMOS technology Implants Semiconductor device modeling Computational modeling Semiconductor process modeling Predictive models Silicon Space technology Costs Space exploration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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