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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ercegovac, M.D. McIlhenny, R. |
| Copyright Year | 2009 |
| Description | Author affiliation: Computer Science Department, Univ. of California at Los Angeles, USA (Ercegovac, M.D.) || Computer Science Department, California State University, Northridge, USA (McIlhenny, R.) |
| Abstract | We present a radix-10 fixed-point digit-recurrence algorithm for square root using limited-precision multipliers, adders, and table-lookups. The algorithm, except in the initialization steps, uses the digit-recurrence algorithm for division with limited-precision primitives. We discuss the proposed square root algorithm, a design, and its FPGA implementation on a Xilinx Virtex-5 FPGA. We present the cost and delay characteristics for precisions of 7 (single-precision), 8, 14 (double-precision), 16, 24, and 32 decimal digits. The costs range from 720 to 2263 LUTs with maximum clock frequencies around 53MHz, and latencies ranging from 133 to 597 ns (with unoptimized routing delays). The proposed scheme uses short (2–3 digit-wide) operators which leads to compact modules, and may have an advantage at the layout level as well as in power optimization. The proposed approach is general and can be adapted to other higher radix square root implementations. Moreover, a combined scheme for division and square root can be efficiently implemented. |
| Starting Page | 935 |
| Ending Page | 939 |
| File Size | 158824 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424458257 |
| ISSN | 10586393 |
| e-ISBN | 9781424458271 |
| DOI | 10.1109/ACSSC.2009.5470015 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-11-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Field programmable gate arrays Delay Costs Table lookup Computer science Error correction Convolution Clocks Frequency |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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