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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kachhwal, P. Rout, B.C. |
| Copyright Year | 2014 |
| Description | Author affiliation: Sch. of VLSI Design & Embedded Syst., Nat. Inst. of Technol., Kurukshetra, India (Kachhwal, P.; Rout, B.C.) |
| Abstract | Square root is a basic arithmetic operation which is used in digital signal processing. Due to complex algorithm it is difficult to implement on FPGA. This paper presents a novel square root algorithm which is based on some ancient Indian mathematics (Vedic mathematics) formula called Dwandwa Yoga. The proposed algorithm uses lowest area. In this paper we are using 24-bit (16bit+8bit) floating point input and 16-bit (8bit+8bit) floating point output. We will discuss the proposed square root algorithm, its hardware description, and its FPGA implementation using Xilinx tool. The cost for this algorithm on the SPARTAN-3E XC3S500E is 173 LUTs (4 input), 90 slices, 99 slice flip flops. The design consumes 90.9 mW power and can be operated at frequency 68.22MHz. This algorithm uses only adders, subtractors and registers which leads to consume less area, less power and high operating frequencies. The proposed algorithm can be implemented on decimal numbers. |
| Starting Page | 158 |
| Ending Page | 162 |
| File Size | 1467242 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479931408 |
| DOI | 10.1109/ICSPCT.2014.6884970 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-07-12 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | SPARTAN-3E Vedic Mathematics Square root FPGA Very large scale integration Educational institutions Dwandwa Yoga Table lookup Xilinx Field programmable gate arrays Clocks |
| Content Type | Text |
| Resource Type | Article |
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