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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gonzalez-Navarro, S. Nannarelli, A. Schulte, M. Tsen, C. |
| Copyright Year | 2009 |
| Description | Author affiliation: University of Málaga, Spain (Gonzalez-Navarro, S.) || Technical University of Denmark, Denmark (Nannarelli, A.) || Nvidia Corporation, USA (Tsen, C.) || University of Wisconsin-Madison, USA (Schulte, M.) |
| Abstract | In this paper, we present the hardware design of a combined decimal and binary floating-point divider, based on specifications in the IEEE 754-2008 Standard for Floating-point Arithmetic. In contrast to most recent decimal divider designs, which are based on the Binary Coded Decimal (BCD) encoding, our divider operates on either 64-bit binary encoded decimal floating-point (DFP) numbers or 64-bit binary floating-point (BFP) numbers. The division approach implemented in our design is based on a digit-recurrence algorithm. We describe the hardware resources shared between the two floating-point datatypes and demonstrate that hardware sharing is advantageous. Compared to a standalone DFP divider, the combined divider has the same worst case delay and 17% more area. |
| Starting Page | 930 |
| Ending Page | 934 |
| File Size | 187360 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424458257 |
| ISSN | 10586393 |
| e-ISBN | 9781424458271 |
| DOI | 10.1109/ACSSC.2009.5470014 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-11-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Encoding Hardware Delay estimation Floating-point arithmetic Algorithm design and analysis Contracts |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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