NDLI: The implementation of an efficient and high-speed inner-product processor

Content Provider	IEEE Xplore Digital Library
Author	Guoping Wang Tull, M.
Copyright Year	2001
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Oklahoma Univ., Norman, OK, USA (Guoping Wang)
Abstract	A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented. The proposed scheme decreases the number of partial products to 50%, compared to other methods, while achieving better speed and area performance and providing pipeline extension opportunities. When modified Booth encoding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require inner-product arithmetic, such as digital filters, correlation and convolution. The proposed design is well suited for VLSI implementation, and it can also be embedded as an inner-product core inside a DSP processor or FPGA-based processor.
Starting Page	1362
Ending Page	1366
File Size	354579
Page Count	5
File Format	PDF
ISBN	078037147X
ISSN	10586393
DOI	10.1109/ACSSC.2001.987714
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Image coding Signal design Signal processing Image processing Digital arithmetic Digital filters Convolution Very large scale integration Digital signal processing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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