NDLI: A reduced-space half-band filter design on an Actel FPGA

Content Provider	IEEE Xplore Digital Library
Author	DeBrunner, L.S. DeBrunner, V. Xiaojuan Hu Demuynck, O. Swartztrauber, A.
Copyright Year	2001
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Oklahoma Univ., Norman, OK, USA (DeBrunner, L.S.)
Abstract	This paper describes the application of our proposed method for low-space implementations of existing half-band FIR filter designs without loss of performance. We achieve greater than 16% reduction of space for a 22/sup nd/ order FIR filter. Further space saving is possible when more efficient multiplications are used. For a fixed-point VLSI implementation, finite wordlength behavior in digital filters is extremely important. Reducing the precision reduces the area consumed in the digital filter implementation at the cost of increasing the filter output quantization noise power. We propose a method suitable for use in VLSI and field programmable gate arrays (FPGAs) by scaling the real filter that reduces the precision of each coefficient. Our idea can be used in conjunction with any FIR digital filter design technique, and thus can be used to reduce the space required for any existing FIR filter.
Starting Page	1237
Ending Page	1240
File Size	470437
Page Count	4
File Format	PDF
ISBN	078037147X
ISSN	10586393
DOI	10.1109/ACSSC.2001.987688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Finite impulse response filter Digital filters Noise reduction IIR filters Very large scale integration Quantization Table lookup Design engineering Application software
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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