NDLI: FPGA power efficient inverse lifting wavelet IP

Content Provider	IEEE Xplore Digital Library
Author	Grangetto, M. Martina, M. Masera, G. Piccinini, G. Vacca, F. Zamboni, M.
Copyright Year	2001
Description	Author affiliation: Dipt. di Elettronica, Politecnico di Torino, Italy (Grangetto, M.)
Abstract	In this paper a power efficient lifting-based wavelet transform IP, well suited for mobile and tetherless applications, is proposed. Recently, reconfigurable architectures, driven by new communication technology challenges and by mobile market explosion have moved developers' interest towards novel IP design strategies. Despite the increasing importance gathered by easily retargetable blocks, a lack of power conscious cores is felt by the developer's community. This IP is intended to be employed as the source coding kernel in many multimedia emerging algorithms. From post-place and route simulation a power dissipation of 36.6 mW has been obtained on a Xilinx XCV200E.
Starting Page	1325
Ending Page	1329
File Size	427720
Page Count	5
File Format	PDF
ISBN	078037147X
ISSN	10586393
DOI	10.1109/ACSSC.2001.987706
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Discrete wavelet transforms Wavelet transforms Hardware Transform coding Laser sintering Reconfigurable architectures Communications technology Explosions Source coding
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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