NDLI: A multiprocessor based packet-switch: performance analysis of the communication infrastructure

Content Provider	IEEE Xplore Digital Library
Author	Tota, S. Casu, M.R. Roch, M.R. Zamboni, M.
Copyright Year	2005
Description	Author affiliation: Dipt. di Elettronica, Politecnico di Torino, Turin, Italy (Tota, S.; Casu, M.R.; Roch, M.R.; Zamboni, M.)
Abstract	The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the network-on-chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found.
Starting Page	172
Ending Page	177
File Size	227782
Page Count	6
File Format	PDF
ISBN	0780393333
ISSN	15206130
DOI	10.1109/SIPS.2005.1579859
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-02
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Network-on-a-chip Availability Power system interconnection Energy consumption Timing Bandwidth Time to market Proposals Multiprocessing systems
Content Type	Text
Resource Type	Article

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