NDLI: A low-power termination criterion for iterative LDPC code decoders

Content Provider	IEEE Xplore Digital Library
Author	Glikiotis, G. Paliouras, V.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Patras Univ., Greece (Glikiotis, G.; Paliouras, V.)
Abstract	This paper introduces a novel criterion for the termination of iterations in iterative LDPC Code decoders. The proposed criterion is amenable for VLSI implementation, and it is here shown that it can enhance previously reported LDPC code decoder architectures substantially, by reducing the corresponding power dissipation. The concept of the proposed criterion is the detection of cycles in the sequences of soft words. The soft-word cycles occur in some cases of low signal-to-noise ratios and indicate that the decoder is unable to decide on a codeword, which in turn results in unnecessary power consumption due to iterations that do not improve the bit error rate. The proposed architecture terminates the decoding process when a soft-word cycle occurs, allowing for substantial power savings at a minimal performance penalty. The proposed criterion is applied to hardware-sharing and parallel decoder architectures.
Starting Page	122
Ending Page	127
File Size	384975
Page Count	6
File Format	PDF
ISBN	0780393333
ISSN	15206130
DOI	10.1109/SIPS.2005.1579850
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-02
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Iterative decoding Energy consumption Message passing Sparse matrices Iterative algorithms Bit error rate Error correction codes Block codes Bipartite graph
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A reduced complexity message passing algorithm with improved performance for LDPC decoding

A shuffled message-passing decoding method for memory-based LDPC decoders

Extended bit-filling and LDPC code design

A scalable decoder architecture for linear congruential LDPC codes

Turbo-like Decoding Algorithm for Structured LDPC codes

A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder

Graph-based message-passing schedules for decoding LDPC codes

Common architecture for decoding turbo and LDPC codes

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

A low-power termination criterion for iterative LDPC code decoders

Similar Documents

A reduced complexity message passing algorithm with improved performance for LDPC decoding

A shuffled message-passing decoding method for memory-based LDPC decoders

Extended bit-filling and LDPC code design

A scalable decoder architecture for linear congruential LDPC codes

Turbo-like Decoding Algorithm for Structured LDPC codes

A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder

Graph-based message-passing schedules for decoding LDPC codes

Common architecture for decoding turbo and LDPC codes

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

A low-power termination criterion for iterative LDPC code decoders