NDLI: Author index

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2015 IEEE Workshop on Signal Processing Systems (SiPS)

2014 IEEE Workshop on Signal Processing Systems (SiPS)

SiPS 2013 Proceedings

2012 IEEE Workshop on Signal Processing Systems

2011 IEEE Workshop on Signal Processing Systems (SiPS)

2010 IEEE Workshop On Signal Processing Systems

2009 IEEE Workshop on Signal Processing Systems

2008 IEEE Workshop on Signal Processing Systems

2007 IEEE Workshop on Signal Processing Systems

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)

Design of multi-gigabit DSP receivers

Driving forces & the technological challenges for SOC development of tomorrow

Perspectives of multimedia SoC

System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs

Design of a DVB-S receiver in FPGA

VLSI implementation of an adaptive equalizer for ATSC digital TV receivers

A low power algorithm for sparse system identification using cross correlation

A frequency channelized adaptive wideband receiver for high-speed links

A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

Energy efficient turbo based space-time coder

An efficient high-speed block turbo code decoding algorithm and hardware architecture design

Hardware-software codesign of a 14.4 MBit - 64 state - Viterbi decoder for an application-specific digital signal processor

Implementation of a wireless multimedia DSP chip for mobile applications

CalmADM/spl trade/: an audio DSP module based on CalmRISC/spl trade/

Subword parallel GF(2/sup m/) ALU: an implementation for a cryptographic processor

AV codec prototype system using a low-power SPXK5SC DSP core

High-performance and energy-efficient heterogeneous subword parallel instructions

Systolic interpolation architectures for soft-decoding Reed-Solomon codes

Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer

Efficient scalable hardware architecture for Montgomery inverse computation in GF(p)

K-nested layered look-ahead method and architectures for high throughput Viterbi decoder

A low power turbo decoder architecture

VLSI implementation of multiplier-free low power baseband filter for CDMA systems

Exploiting value locality for secure-energy aware communication

A generalized robust wideband array beamformer

Calculation the infinite norm ball of constant modulus receivers by D-K iterations

A robust beamformer for OFDM based WLANs against burst interference

Reconfigurable discrete wavelet transform architecture for advanced multimedia systems

A real time, low latency, hardware implementation of the 2D discrete wavelet transformation for streaming image applications

A cost-effective implementation of object-based motion estimation

Face tracking with an efficient use of the ME engine in a video processor

Affine schemes in mesh-based video motion compensation

A zero-value prediction technique for fast DCT computation

An MPEG-4 facial animation parameters generation system

Optimal data transfer and buffering schemes for JPEG2000 encoder

VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder

HiBRID-SoC: a multi-core SoC architecture for multimedia signal processing

A technique for reducing complexity of recursive motion estimation algorithms

A novel vario-power architecture of motion estimation using a content based subsample algorithm

Accelerating mobile video applications using Intel/sup /spl reg// Wireless MMX/spl trade/ technology

Design of low error fixed-width squarer

FPGA implementation of Kalman low-pass filter for applications in sigma-delta (/spl Sigma/-/spl Delta/) demodulation

A digit-pipelined direct digital frequency synthesis architecture

Implementation of complex-arithmetic heterodyne filter

A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation

Acoustic echo cancellation using blind source separation

Task concurrency analysis and exploration of visual texture decoder on a heterogeneous platform

Dynamic wordlength variation for low-power 3D graphics texture mapping

Trellis-based systolic multi-layer stereo matching

Recursive filtering on SIMD architectures

High performance SEED processors

Efficient IMDCT core designs for audio signal processing

VLIW SIMD architecture based implementation of a multi-level dot diffusion algorithm

Novel DSP architecture for OFDM modem systems

Low-power floating-point encoding for signal processing applications

A new approach to dynamically trade off performance and energy consumption in wireless communication systems

Battery-friendly design of signal processing algorithms

Utilizing synthesis methods in accurate system-level exploration of heterogeneous embedded systems

Automatic coarse-grain partitioning and automatic code generation for heterogeneous architectures

A mixed QoS SDRAM controller for FPGA-based high-end image processing

Quality-aware memory controller for multimedia platform SoC

Viterbi decoding on a coprocessor architecture with vector parallelism

Efficient direct 2D architecture for lifted biorthogonal DWT

VLSI architecture for discrete wavelet transform based on B-spline factorization

Energy aware distributed arithmetic DCT architectures

Efficient shape-adaptive zero tree coding scheme and its FPGA implementation for DWT based progressive coding

An efficient implementation of hierarchical image coding

Methodology for refinement and optimization of dynamic memory management for embedded systems in multimedia applications

Hierarchical DSP architectural synthesis and scheduling solution for "IRIS"

Modeling of block-based DSP systems

Receiver synthesis for nonlinearly amplified OFDM signal

IEEE Workshop on Signal Processing Systems

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)

2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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