NDLI: Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer

Content Provider	IEEE Xplore Digital Library
Author	Seok-Jun Lee Shanbhag, N.R. Singer, A.C.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA (Seok-Jun Lee; Shanbhag, N.R.; Singer, A.C.)
Abstract	We present an area-efficient MAP-based turbo equalizer VLSI architecture by proposing a symbol-based soft-input soft-output (SISO) kernel which processes one multi-bit symbol in every clock cycle. The symbol-based SISO hardware can be shared by the equalizer and decoder, thereby reducing silicon area. Further, by introducing block-interleaved computation in the add-compare-select recursions, the critical path delay is reduced, thereby improving throughput. Experimental results with QPSK modulation and K/spl sup/5 encoder demonstrate that the proposed area-efficient architecture achieves area savings of 47% with 11% throughput gain in a 0.25 /spl mu/m CMOS process. It is also shown that the throughput is improved by 79% via block-interleaved computation with an area savings of 25%.
Sponsorship	IEEE Signal Processing Soc. IEEE Circuits & Syst. Soc
Starting Page	87
Ending Page	92
File Size	364959
Page Count	6
File Format	PDF
ISBN	0780377958
ISSN	15206130
DOI	10.1109/SIPS.2003.1235649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Equalizers Throughput Computer architecture Kernel Clocks Hardware Decoding Silicon Delay
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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