NDLI: Recursive filtering on SIMD architectures

Content Provider	IEEE Xplore Digital Library
Author	Schaffer, R. Hosemann, M. Merker, R. Fettweis, G.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng. & Inf. Technol., Dresden Univ. of Technol., Germany (Schaffer, R.; Hosemann, M.; Merker, R.; Fettweis, G.)
Abstract	Recursive filters are used frequently in digital signal processing. They can be implemented in dedicated hardware or in software on a digital signal processor (DSP). Software. solutions often are preferable for their speed of implementation and flexibility. However, contemporary DSPs are mostly not fast enough to perform filtering for high data-rates or large filters. A method to increase the computational power of a DSP without sacrificing efficiency is to use multiple processor elements controlled by the single-instruction multiple-data (SIMD) paradigm. The parallelization of recursive algorithms is difficult, because of the data dependencies. We use design methods for parallel processor arrays to realize implementations that can be used on a parallel DSP. Further, we focus on the partitioning of the algorithm so that the realization can be used for different architectures. Consequences for the architecture are also considered. The infinite impulse response (IIR) filter, the most familiar recursive filter, is used in the description of the design process.
Sponsorship	IEEE Signal Processing Soc. IEEE Circuits & Syst. Soc
Starting Page	263
Ending Page	268
File Size	365379
Page Count	6
File Format	PDF
ISBN	0780377958
ISSN	15206130
DOI	10.1109/SIPS.2003.1235680
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-27
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Filtering Digital signal processing IIR filters Partitioning algorithms Signal processing algorithms Computer architecture Digital filters Hardware Digital signal processors Process control
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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