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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jun Jin Kong Parhi, K.K. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., USA (Jun Jin Kong; Parhi, K.K.) |
| Abstract | A novel K-nested layered look-ahead method and its corresponding architectures, which pack K trellis steps into one step (where K is the encoder constraint length) and combine two look-ahead sub-trellises in a layered manner, are proposed for a high throughput Viterbi decoder. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select computations to all trellis layers. It leads to a regular and simple architecture for the Viterbi decoding algorithm. The proposed method can be implemented in a partly or fully parallel manner and can be used for a high throughput Viterbi decoder. The main advantage of the proposed design is that it has the least latency among all look-ahead Viterbi decoders for a given level of parallelism. |
| Sponsorship | IEEE Signal Processing Soc. IEEE Circuits & Syst. Soc |
| Starting Page | 99 |
| Ending Page | 104 |
| File Size | 431155 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780377958 |
| ISSN | 15206130 |
| DOI | 10.1109/SIPS.2003.1235651 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-08-27 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Throughput Viterbi algorithm Iterative decoding Computer architecture Distributed computing Concurrent computing Delay Parallel processing Feedback loop Pipeline processing |
| Content Type | Text |
| Resource Type | Article |
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