NDLI: Efficient algorithm and architecture designs for MPEG-4 shape adaptive video object coding

Content Provider	IEEE Xplore Digital Library
Author	Yin-Tsung Hwang Shi-Shen Wang Yun-Chiang Wang
Copyright Year	2001
Description	Author affiliation: Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan (Yin-Tsung Hwang)
Abstract	An efficient algorithm and its VLSI architecture design for real-time shape adaptive zerotree coding (SA-ZTC) are presented. The proposed algorithm takes the DWT coefficients of the image as input and encodes the quantized coefficients efficiently to achieve the data compression. Most other wavelet coefficient-coding algorithms cannot provide real-time computation because they use multi-pass algorithms to decide the zerotrees formed by the wavelet coefficients. In contrast, the proposed SA-ZTC adopts a one pass algorithm and thus greatly reduces the computation time for real-time processing. Besides, the proposed architecture can be equally applied to both whole image coding without shape mask (eg, JPEG 2000) and object-based image coding with shape mask (eg, MPEG-4). Experimental results indicate the proposed algorithm can achieve better coding efficiency than the widely adopted EZW and the performance is close to the multi-pass SPHIT algorithm. The derived architecture design is shown to be hardware cost-effective and capable of delivering real-time processing.
Sponsorship	IEEE Signal Process. Soc.
Starting Page	297
Ending Page	308
File Size	683799
Page Count	12
File Format	PDF
ISBN	0780371453
ISSN	15206130
DOI	10.1109/SIPS.2001.957357
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-26
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis MPEG 4 Standard Shape Computer architecture Image coding Very large scale integration Discrete wavelet transforms Data compression Wavelet coefficients Hardware
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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