NDLI: An efficient linear-phase FIR filter architecture design for wireless embedded system

Content Provider	IEEE Xplore Digital Library
Author	Shyh Feng Lin Sheng-Chieh Huang Feng-Sung Yang Chung-Wei Ku Liang-Gee Chen
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Shyh Feng Lin)
Abstract	This paper presents a novel approach for implementing power-efficient finite impulse response (FIR) filters that require less power consumption than traditional FIR filter implementations in wireless embedded systems. The proposed schemes impose to the direct form and achieve a certain reduction in the power consumption. A novel retimed structure and balanced modularized techniques are introduced and used to reduce the critical path to achieve hardware efficiency. A novel separated signed processing data flow scheme with modifying CSD (canonical signed digit) representation is also introduced and used to reduce the transition, which is the main source of power consumption. The combination of the proposed methods gives up to 71% reduction in power consumption with a slight area overhead.
Sponsorship	IEEE Signal Process. Soc.
Starting Page	193
Ending Page	200
File Size	457676
Page Count	8
File Format	PDF
ISBN	0780371453
ISSN	15206130
DOI	10.1109/SIPS.2001.957347
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-26
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Embedded system Energy consumption Adders Pipeline processing Digital signal processing Design engineering Power engineering and energy Hardware Noise reduction
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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