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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Leibo Liu Xuejin Wang Hongying Meng Li Zhang Zhihua Wang Hongyi Chen |
| Copyright Year | 2002 |
| Description | Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Leibo Liu) |
| Abstract | The Discrete Wavelet Transform (DWT) is the basis for many image compression techniques, such as JPEG2000, MPEG-4, etc. The Spatial Combinative Lifting Algorithm (SCLA) based 2-D DWT/IDWT requires fewer computations than the conventional Lifting Based Implementation (LBI). In comparison with the LBI, SCLA with the 9/7 filter has 7/12 the number of multiplications. This paper proposes a novel VLSI architecture to compute multilevel SCLA based 2-D DWT/IDWT with the 9/7 filter. The line based transform is integrated with the SCLA scheme to reduce the hardware cost and achieve higher hardware utilization. Efficient organization of six line-buffer memories is used to address the high memory bandwidth requirements. This architecture can be used as a compact and efficient core for JPEG2000 VLSI implementation and various real-time image/video applications. |
| Starting Page | 299 |
| Ending Page | 304 |
| File Size | 533636 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780376900 |
| DOI | 10.1109/APCCAS.2002.1115240 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-28 |
| Publisher Place | Indonesia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Discrete wavelet transforms Computer architecture Filters Hardware Image coding Transform coding MPEG 4 Standard Costs Bandwidth |
| Content Type | Text |
| Resource Type | Article |
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