NDLI: Hybrid designs for non-volatile embedded memory cells

Content Provider	IEEE Xplore Digital Library
Author	Wei Wei Lombardi, F. Namba, K.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA (Wei Wei; Lombardi, F.) \|\| Grad. Sch. of Adv. Integration Sci., Chiba Univ., Chiba, Japan (Namba, K.)
Abstract	Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations; this scheme is often referred to as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM; an Oxide Resistive Random Access Memory (RRAM) is utilized as non-volatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript; they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge and SER analysis) and variations. Extensive simulation results using nanometric PTMs are provided.
Starting Page	1206
Ending Page	1209
File Size	307841
Page Count	4
File Format	PDF
e-ISBN	9781467381567
DOI	10.1109/NANO.2015.7388845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Transistors Power dissipation Delays SRAM cells Resistance Non-volatile memory component Memory design Static and dynamic memory cells Low power Hybrid memory
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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