NDLI: Ultraflat nanopores for wafer-scale molecular-electronic applications

Content Provider	IEEE Xplore Digital Library
Author	Puebla-Hellmann, G. Mayor, M. Lortscher, E.
Copyright Year	2015
Description	Author affiliation: Dept. of Chem., Uni Basel, Basel, Switzerland (Puebla-Hellmann, G.; Mayor, M.) \|\| Adv. Micro Integration, IBM Res. - Zurich, Zurich, Switzerland (Lortscher, E.)
Abstract	Electronic building-blocks whose electrical characteristics are based on the intrinsic transport mechanism of a self-assembled monolayer (SAM) of molecules have the potential to offer novel and application-tailored functionality, achievable via synthetic chemistry approaches, while being less sensitive to microscopic fluctuations compared to single-molecule electronics. To implement such molecular building blocks and exploit their full potential in a solid-state architecture, a scalable platform compatible with standard fabrication processes is necessary, which guarantees molecular integrity throughout the entire process flow. Targeting a platform where the SAM is integrated in a vertical orientation, we present a fabrication process that yields pores with ultrasmooth platinum bottom electrodes and diameters ranging from 100 õm down to 30 nm. This scalable process is demonstrated on 4" wafers with several 10'000 pores per wafer and will allow the statistical study of molecular transport properties based on large datasets under various conditions.
Starting Page	1197
Ending Page	1201
File Size	305517
Page Count	5
File Format	PDF
e-ISBN	9781467381567
DOI	10.1109/NANO.2015.7388843
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-27
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Platinum Electrodes Rough surfaces Surface roughness Surface treatment Fabrication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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