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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wan-Cheng Zhang Nan-Jian Wu |
| Copyright Year | 2007 |
| Description | Author affiliation: State Key Labroatory of Superlattice & Microstructures, Chinese Acad. of Sci., Beijing (Wan-Cheng Zhang; Nan-Jian Wu) |
| Abstract | This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12times12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600 MHz with 400 nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits. |
| Starting Page | 690 |
| Ending Page | 694 |
| File Size | 384765 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424406074 |
| DOI | 10.1109/NANO.2007.4601283 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-08-02 |
| Publisher Place | Hong Kong |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Adders Tin Logic gates Integrated circuit modeling Power dissipation Simulation Performance evaluation PD2,3 adder Fast adder Multiplier Single-electron turnstile Single-electron logic |
| Content Type | Text |
| Resource Type | Article |
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