NDLI: NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

Content Provider	IEEE Xplore Digital Library
Author	Pugsley, S.H. Jestes, J. Huihui Zhang Balasubramonian, R. Srinivasan, V. Buyuktosunoglu, A. Davis, A. Feifei Li
Copyright Year	2014
Description	Author affiliation: Univ. of Utah, Salt Lake City, UT, USA (Pugsley, S.H.; Jestes, J.; Huihui Zhang; Balasubramonian, R.; Davis, A.; Feifei Li) \|\| T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA (Srinivasan, V.; Buyuktosunoglu, A.)
Abstract	While Processing-in-Memory has been investigated for decades, it has not been embraced commercially. A number of emerging technologies have renewed interest in this topic. In particular, the emergence of 3D stacking and the imminent release of Micron's Hybrid Memory Cube device have made it more practical to move computation near memory. However, the literature is missing a detailed analysis of a killer application that can leverage a Near Data Computing (NDC) architecture. This paper focuses on in-memory MapReduce workloads that are commercially important and are especially suitable for NDC because of their embarrassing parallelism and largely localized memory accesses. The NDC architecture incorporates several simple processing cores on a separate, non-memory die in a 3D-stacked memory package; these cores can perform Map operations with efficient memory access and without hitting the bandwidth wall. This paper describes and evaluates a number of key elements necessary in realizing efficient NDC operation: (i) low-EPI cores, (ii) long daisy chains of memory devices, (iii) the dynamic activation of cores and SerDes links. Compared to a baseline that is heavily optimized for MapReduce execution, the NDC design yields up to 15X reduction in execution time and 18X reduction in system energy.
Sponsorship	IEEE Comput. Soc.
Starting Page	190
Ending Page	200
File Size	843312
Page Count	11
File Format	PDF
ISBN	9781479936045
e-ISBN	9781479936069
DOI	10.1109/ISPASS.2014.6844483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth Three-dimensional displays Databases Random access memory Central Processing Unit Memory management
Content Type	Text
Resource Type	Article

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