NDLI: Exploiting spatial architectures for edit distance algorithms

Content Provider	IEEE Xplore Digital Library
Author	Tithi, J.J. Crago, N.C. Emer, J.S.
Copyright Year	2014
Description	Author affiliation: VSSAD, Intel Corp., Hudson, MA, USA (Crago, N.C.; Emer, J.S.) \|\| Stony Brook Univ., Stony Brook, NY, USA (Tithi, J.J.)
Abstract	In this paper, we demonstrate the ability of spatial architectures to significantly improve both runtime performance and energy efficiency on edit distance, a broadly used dynamic programming algorithm. Spatial architectures are an emerging class of application accelerators that consist of a network of many small and efficient processing elements that can be exploited by a large domain of applications. In this paper, we utilize the dataflow characteristics and inherent pipeline parallelism within the edit distance algorithm to develop efficient and scalable implementations on a previously proposed spatial accelerator. We evaluate our edit distance implementations using a cycle-accurate performance and physical design model of a previously proposed triggered instruction-based spatial architecture in order to compare against real performance and power measurements on an x86 processor. We show that when chip area is normalized between the two platforms, it is possible to get more than a 50× runtime performance improvement and over 100× reduction in energy consumption compared to an optimized and vectorized x86 implementation. This dramatic improvement comes from leveraging the massive parallelism available in spatial architectures and from the dramatic reduction of expensive memory accesses through conversion to relatively inexpensive local communication.
Sponsorship	IEEE Comput. Soc.
Starting Page	23
Ending Page	34
File Size	1733008
Page Count	12
File Format	PDF
ISBN	9781479936045
e-ISBN	9781479936069
DOI	10.1109/ISPASS.2014.6844458
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Pipelines Field programmable gate arrays Parallel processing Signal processing algorithms Matrix converters Dynamic programming
Content Type	Text
Resource Type	Article

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