NDLI: BarrierPoint: Sampled simulation of multi-threaded applications

Content Provider	IEEE Xplore Digital Library
Author	Carlson, T.E. Heirman, W. Van Craeynest, K. Eeckhout, L.
Copyright Year	2014
Description	Author affiliation: ExaSci. Lab., Intel, Leuven, Belgium (Heirman, W.) \|\| Ghent Univ., Ghent, Belgium (Carlson, T.E.; Van Craeynest, K.; Eeckhout, L.)
Abstract	Sampling is a well-known technique to speed up architectural simulation of long-running workloads while maintaining accurate performance predictions. A number of sampling techniques have recently been developed that extend well-known single-threaded techniques to allow sampled simulation of multi-threaded applications. Unfortunately, prior work is limited to non-synchronizing applications (e.g., server throughput workloads); requires the functional simulation of the entire application using a detailed cache hierarchy which limits the overall simulation speedup potential; leads to different units of work across different processor architectures which complicates performance analysis; or, requires massive machine resources to achieve reasonable simulation speedups. In this work, we propose BarrierPoint, a sampling methodology to accelerate simulation by leveraging globally synchronizing barriers in multi-threaded applications. BarrierPoint collects microarchitecture-independent code and data signatures to determine the most representative inter-barrier regions, called barrierpoints. BarrierPoint estimates total application execution time (and other performance metrics of interest) through detailed simulation of these barrierpoints only, leading to substantial simulation speedups. Barrierpoints can be simulated in parallel, use fewer simulation resources, and define fixed units of work to be used in performance comparisons across processor architectures. Our evaluation of BarrierPoint using NPB and Parsec benchmarks reports average simulation speedups of 24.7× (and up to 866.6×) with an average simulation error of 0.9% and 2.9% at most. On average, BarrierPoint reduces the number of simulation machine resources needed by 78×.
Sponsorship	IEEE Comput. Soc.
Starting Page	2
Ending Page	12
File Size	4410954
Page Count	11
File Format	PDF
ISBN	9781479936045
e-ISBN	9781479936069
DOI	10.1109/ISPASS.2014.6844456
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Benchmark testing Vectors Load modeling Microarchitecture Instruction sets Synchronization
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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