NDLI: Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems

Content Provider	IEEE Xplore Digital Library
Author	Ghosh, M. Lee, H.-H.S.
Copyright Year	2007
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA (Ghosh, M.; Lee, H.-H.S.)
Abstract	This paper proposes virtual exclusion, an architectural technique to reduce leakage energy in the L2 caches for cache-coherent multiprocessor systems. This technique leverages two previously proposed circuits techniques - gated $V_{dd}$ and drowsy cache, and proposes a low cost, easily implementable scheme for cache-coherent multiprocessor systems. The virtual exclusion scheme saves leakage energy by keeping the data portion of repetitive cache lines off in the large higher level caches while still manages to maintain multi-level Inclusion, an essential property for an efficient implementation of conventional cache coherence protocols. By exploiting the existing state information in the snoop-based cache coherence protocol, there is almost no extra hardware overhead associated with our scheme. In our experiments, the SPLASH-2 multiprocessor benchmark suite was correctly executed under the new Virtual Exclusion policy and showed an up to 72% savings of leakage energy (46% for SMP and 35% for multicore in L2 on average) over a baseline drowsy L2 cache.
Starting Page	1
Ending Page	8
File Size	277114
Page Count	8
File Format	PDF
ISBN	9781424418893
ISSN	15219097
DOI	10.1109/ICPADS.2007.4447739
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-05
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessing systems Circuits Threshold voltage Energy consumption Random access memory CMOS technology Power engineering and energy Leakage current Turning Multicore processing
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

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