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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vaidyanathan, K. Huang, W. Chai, L. Panda, D.K. |
| Copyright Year | 2007 |
| Description | Author affiliation: Comput. Sci. & Eng., Ohio State Univ., Columbus, OH (Vaidyanathan, K.; Huang, W.; Chai, L.; Panda, D.K.) |
| Abstract | Memory copies for bulk data transport incur large overheads due to CPU stalling, small register-size data movement, etc. Intel's I/O Acceleration Technology offers an asynchronous memory copy engine in kernel space which alleviates such overheads. In this paper, we propose a set of designs for asynchronous memory operations in user space for both single process (as an offloaded memcpy()) and lPC using the copy engine. We analyze our design based on overlap efficiency, performance and cache utilization. Our microbenchmark results show that using the copy engine for performing memory copies can achieve close to 87% overlap with computation. Further, the copy engine improves the copy latency of bulk memory data transfers by 50% and avoids cache pollution effects. With the emergence of multi-core architectures, the support for asynchronous memory operations holds a lot of promise in reducing the gap between the memory and processor performance. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 295667 |
| Page Count | 8 |
| File Format | |
| ISBN | 1424409098 |
| DOI | 10.1109/IPDPS.2007.370479 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-03-26 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Engines Space technology Acceleration Kernel Linear predictive coding Performance analysis Delay Pollution Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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