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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Brito, A.V. Kuehnle, M. Melcher, E.U.K. Becker, J. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electr. Eng., Fed. Univ. of Campina Grande (Brito, A.V.) |
| Abstract | An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for dynamic reconfiguration. The presented approach can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level (RTL), if the dynamic system behavior is desired to be observed at signal level. The reconfigurable processor can be easily set to model the desired architecture in a behavioral but reasonable way. An example is presented where a XPP processor is implemented and simulated, executing typical applications. The resulting statistics assist either in the choice of the best cost/benefit configuration area that should be available on chip, or in the choice of the target architecture itself. |
| Starting Page | 1 |
| Ending Page | 7 |
| File Size | 177824 |
| Page Count | 7 |
| File Format | |
| ISBN | 1424409098 |
| DOI | 10.1109/IPDPS.2007.370375 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-03-26 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Object oriented modeling Runtime Power system modeling Switches System-on-a-chip System testing Hardware design languages Kernel Embedded software Registers |
| Content Type | Text |
| Resource Type | Article |
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