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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Silva, M.L. Ferreira, J.C. |
| Copyright Year | 2006 |
| Description | Author affiliation: FEUP/DEEC, Porto (Silva, M.L.; Ferreira, J.C.) |
| Abstract | The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing |
| File Size | 887402 |
| File Format | |
| ISBN | 1424400546 |
| DOI | 10.1109/IPDPS.2006.1639447 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-04-25 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Hardware Central Processing Unit Runtime Reconfigurable logic Circuits Pattern matching Image processing Contracts Scholarships |
| Content Type | Text |
| Resource Type | Article |
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