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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Collins, R. Alegre, F. Xiaotong Zhuang Pande, S. |
| Copyright Year | 2006 |
| Description | Author affiliation: Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA (Collins, R.; Alegre, F.; Xiaotong Zhuang; Pande, S.) |
| Abstract | Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encountering long latency memory accesses and this way the parallelism and memory access can be overlapped. Context switches in the typical network processor architectures such as the IXP are designed to be very fast. However, the low overhead is partly achieved by leaving register management to programs, with minimal support from the hardware. The complexity of the multi-engine, multi-threaded environment makes manual register management a daunting task, which is better left to a compiler. However, a purely static analysis is unable to achieve full utilization of the register file due to conservative estimates of liveness. A register that is live across a context switch point must be considered live for the duration of all other threads, and so it must be assumed to be unavailable to other threads. In addition, aliasing further reduces the effectiveness of static analysis. The net effect is a large number of idle cycles that are still present after static optimization. We propose a dynamic solution that requires minimal software and hardware support. On the software side, we take a pre-allocated binary file and annotate the potential context switch instructions with information about the dead registers. On the hardware side, we try to rename the transfer registers and addresses to dead general purpose registers and update the usage of registers. We then replace the long-latency memory instructions with fast move instructions in the architecture using the dynamic context. The results show up to 51% reduction in idle cycles and up to H% increase in the throughput for hand coded applications on Intel IXP 1200 network processor |
| File Size | 187825 |
| File Format | |
| ISBN | 1424400546 |
| DOI | 10.1109/IPDPS.2006.1639291 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-04-25 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Dynamic compiler Registers Yarn Switches Hardware Parallel processing Delay Programming profession Program processors Computer network management |
| Content Type | Text |
| Resource Type | Article |
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