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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | El-Moursy, A. Garg, R. Albonesi, D.H. Dwarkadas, S. |
| Copyright Year | 2006 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Rochester Univ., NY (El-Moursy, A.; Garg, R.) |
| Abstract | The industry is rapidly moving towards the adoption of chip multi-processors (CMPs) of simultaneous multi-threaded (SMT) cores for general purpose systems. The most prominent use of such processors, at least in the near term, is as job servers running multiple independent threads on the different contexts of the various SMT cores. In such an environment, the co-scheduling of phases from different threads plays a significant role in the overall throughput. Less throughput is achieved when phases from different threads that conflict for particular hardware resources are scheduled together, compared with the situation where compatible phases are co-scheduled on the same SMT core. Achieving the latter requires precise per-phase hardware statistics that the scheduler can use to rapidly identify possible incompatibilities among phases of different threads, thereby avoiding the potentially high performance cost of inter-thread contention. In this paper, we devise phase co-scheduling policies for a dual-core CMP of dual-threaded SMT processors. We explore a number of approaches and find that the use of ready and in-flight instruction metrics permits effective co-scheduling of compatible phases among the four contexts. This approach significantly outperforms the worst static grouping of threads, and very closely matches the best static grouping, even outperforming it by as much as 7% |
| File Size | 397765 |
| File Format | |
| ISBN | 1424400546 |
| DOI | 10.1109/IPDPS.2006.1639376 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-04-25 |
| Publisher Place | Greece |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Yarn Surface-mount technology Processor scheduling Throughput Microprocessors Hardware Job shop scheduling Decoding Computer science Laboratories |
| Content Type | Text |
| Resource Type | Article |
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